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DSB75 Development Support Board Rev. B1 Hardware Description
Strictly confidential / Released
s
DSB75_hd_v08 Page 84 of 94 29.09.2005
8.2 Circuit Diagrams of DSB75
06.07.2004
netlist1
VUSB_3V3
/sheet1 9 B
/sheet1 10 C
VUSB_IN
/sheet1 2 G
/sheet1 4 B
/sheet1 5 C
1:1
TOP HIERARCHY LEVEL
DSB75
B1
SCHEMATIC
/sheet1 2 F
VDDLP
/sheet1 2 B
/sheet1 2 E
/sheet4 1 F
VDD_EN
/sheet4 13 A
/sheet2 8 E
VEXT
/sheet1 3 E
/sheet1 2 B
/sheet5 9 D
VMIC
/sheet1 4 B
/sheet1 3 F
/sheet7 8 B
VMIC_I
/sheet7 8 B
/sheet7 6 B
VSENSE
/sheet1 4 B
/sheet1 3 F
/sheet6 5 B
VSIM
/sheet6 4 E
AD1_IN
/sheet1 4 D
/sheet1 2 G
/sheet5 10 B
AD2_IN
/sheet1 4 C
/sheet1 2 G
3V0
/sheet1 10 E
/sheet4 2 D
/sheet4 6 D
/sheet4 3 B
/sheet4 8 B
/sheet2 12 C
/sheet2 5 A
/sheet2 8 E
/sheet2 1 D
/sheet2 12 A
/sheet2 12 A
/sheet1 2 E
/sheet6 2 D
CC CLK
/sheet1 4 B
/sheet1 2 F
/sheet5 6 B
CC GND
/sheet1 1 F
/sheet2 2 A
/sheet2 9 E
/sheet2 8 D
/sheet2 12 C
/sheet2 5 D
/sheet2 6 E
/sheet2 9 F
3V3_4V5
/sheet6 4 D
/sheet4 11 A
5V0
/sheet7 10 B
/sheet7 8 A
/sheet7 11 F
/sheet5 4 C
/sheet5 7 D
/sheet4 7 A
/sheet4 13 A
/sheet4 4 B
5V0_I
/sheet7 11 C
/sheet7 12 B
6V6
/sheet7 7 A
/sheet2 10 B
/sheet2 5 B
CTS1
/sheet1 2 C
/sheet1 3 E
/sheet3 3 D
/sheet2 5 E
CTS1_I
/sheet5 10 B
AGND
/sheet1 2 C
/sheet1 3 F
/sheet7 8 C
AG ND_I
/sheet7 8 C
/sheet7 6 C
ASC_EN1
/sheet2 12 B
/sheet2 9 E
ASC_EN2
/sheet2 12 C
/sheet2 9 F
ASC_SD
/sheet2 1 F
/sheet2 12 A
/sheet2 12 C
BATT+
/sheet1 4 D
/sheet6 5 B
/sheet6 4 D
BATTEMP
/sheet1 2 C
/sheet2 13 B
DTR0
/sheet1 2 B
/sheet1 3 E
/sheet2 10 B
/sheet2 6 B
EMERG_RST
/sheet1 2 C
/sheet1 2 D
/sheet5 4 B
/sheet5 4 B
/sheet5 6 B
/sheet5 6 B
CC IN
/sheet1 4 A
/sheet1 2 F
/sheet5 6 B
CC IO
/sheet1 4 A
/sheet1 2 F
/sheet5 6 B
CC RST
/sheet1 4 A
/sheet1 2 F
/sheet5 6 B
CH ARGEG AT E
/sheet1 2 B
/sheet1 2 E
/sheet6 1 C
CTS0
/sheet1 2 C
/sheet1 3 E
EPP2
/sheet1 4 B
/sheet1 3 F
/sheet7 4 E
EPP2_I
/sheet7 5 E
/sheet7 6 C
GPIO10_I
/sheet3 5 D
/sheet2 9 D
DAC_OUT
/sheet1 4 D
/sheet1 3 G
/sheet5 7 A
DC D0
/sheet1 2 C
/sheet1 3 E
/sheet2 10 B
/sheet2 5 B
DM_B
/sheet1 5 C
/sheet1 11 A
DP_B
/sheet1 5 D
/sheet1 11 A
DSR0
/sheet1 2 B
/sheet1 3 E
/sheet2 10 B
/sheet2 5 B
DTR
/sheet4 1 F
/sheet4 2 E
GPIO7_I
/sheet4 12 F
/sheet4 14 F
GPIO7_SPI
/sheet5 7 C
/sheet4 12 E
GPIO8
/sheet1 3 F
/sheet1 7 B
/sheet4 1 G
EPN1
/sheet1 4 A
/sheet1 3 F
/sheet7 4 F
EPN1_I
/sheet7 5 F
/sheet7 8 D
EPN2
/sheet1 4 B
/sheet1 3 F
/sheet7 4 E
EPN2_I
/sheet7 5 E
/sheet7 6 D
EPP1
/sheet1 4 A
/sheet1 3 F
/sheet7 4 E
EPP1_I
/sheet7 5 E
/sheet7 8 D
/sheet5 5 D
I2C_CLK_5V
/sheet5 5 C
/sheet5 7 C
I2C_D AT_3V
/sheet5 7 C
/sheet5 7 C
/sheet5 5 D
/sheet4 14 G
/sheet4 12 G
GPIO1_I
/sheet4 12 C
/sheet4 14 C
GPIO2_I
/sheet4 12 D
/sheet4 14 D
GPIO3_I
/sheet4 14 D
/sheet4 12 D
GPIO4_I
/sheet4 12 E
/sheet4 14 D
GPIO5_I
/sheet4 14 E
/sheet4 12 E
GPIO6_I
/sheet4 12 E
/sheet4 14 E
GPIO7
/sheet1 4 C
/sheet1 3 G
/sheet4 12 F
/sheet7 6 C
MICP1
/sheet1 2 D
/sheet1 3 F
/sheet7 4 G
MICP1_I
/sheet7 5 G
/sheet7 8 C
/sheet1 4 C
/sheet1 2 G
/sheet4 12 F
/sheet4 2 E
GPIO8_I
/sheet4 14 F
/sheet4 12 F
GPIO8_SPI
/sheet5 7 C
/sheet4 12 F
GPIO9_I
/sheet4 12 F
/sheet4 14 F
I2CC LK
/sheet1 4 B
/sheet1 2 G
/sheet5 1 C
I2CD AT
/sheet1 4 B
/sheet1 3 G
/sheet5 1 D
I2C_CLK_3V
/sheet5 7 C
/sheet5 7 C
/sheet1 3 E
/sheet2 10 B
/sheet2 5 B
RTS1
/sheet1 2 C
/sheet1 3 E
/sheet3 3 C
/sheet2 5 E
I2C_D AT_5V
/sheet5 7 C
/sheet5 5 D
IGT
/sheet1 2 C
/sheet1 3 F
/sheet4 1 F
ISENSE
/sheet1 4 B
/sheet1 2 F
/sheet6 5 B
MICN1
/sheet1 2 D
/sheet1 3 F
/sheet7 4 G
MICN1_I
/sheet7 5 G
/sheet7 8 D
MICN2
/sheet1 4 A
/sheet1 3 F
/sheet7 4 F
MICN2_I
/sheet7 5 F
RXD2_I
/sheet4 12 F
/sheet2 9 D
SD_CLK
/sheet1 4 B
/sheet1 2 G
/sheet4 2 E
/sheet4 11 E
MICP2
/sheet1 2 D
/sheet1 3 F
/sheet7 4 F
MICP2_I
/sheet7 5 F
/sheet7 6 C
POWER
/sheet6 1 A
/sheet6 4 E
PWR_IND
/sheet1 4 D
/sheet1 3 G
/sheet4 2 D
/sheet2 5 E
/sheet2 5 B
/sheet2 9 E
RIN G0
/sheet1 2 B
/sheet1 3 E
/sheet2 10 B
/sheet2 5 B
RTS0
/sheet1 2 B
SD_D1_I
/sheet4 12 D
/sheet3 3 D
SD_D2
/sheet1 4 C
/sheet1 3 G
/sheet4 2 E
/sheet4 11 D
RTS1_ I
/sheet3 5 C
/sheet2 10 D
RXD0
/sheet1 2 B
/sheet1 2 E
/sheet2 9 B
RXD0_I
/sheet2 10 B
/sheet2 7 B
/sheet2 5 B
RXD1
/sheet1 2 C
/sheet1 2 E
/sheet3 2 C
/sheet2 5 E
RXD1_I
/sheet3 5 C
/sheet2 9 D
RXD2_GPIO9
/sheet1 4 C
/sheet1 3 G
/sheet4 11 F
/sheet2 5 E
/sheet5 7 C
/sheet3 3 C
SPI2_DO
/sheet5 7 C
/sheet3 3 D
SPI2_SCLK
/sheet5 7 C
/sheet3 3 C
SD_CLK_I
/sheet4 12 E
/sheet3 3 D
SD_CMD
/sheet1 4 C
/sheet1 2 G
/sheet4 11 E
/sheet4 2 E
SD_CMD_I
/sheet4 12 E
/sheet3 3 D
SD_D0
/sheet1 4 C
/sheet1 3 G
/sheet4 2 E
/sheet4 11 C
SD_D0_I
/sheet4 12 C
/sheet3 3 D
SD_D1
/sheet1 4 C
/sheet1 3 G
/sheet4 2 E
/sheet4 11 D
TXD2_GPIO10
/sheet1 4 C
/sheet1 2 G
/sheet4 11 G
/sheet2 5 E
TXD2_I
/sheet4 12 G
/sheet2 10 D
SD_D2_I
/sheet4 12 D
/sheet3 3 E
SD_D3
/sheet1 4 C
/sheet1 3 G
/sheet4 2 E
/sheet4 11 D
SD_D3_I
/sheet4 12 D
/sheet3 3 D
SD_DET
/sheet1 4 C
/sheet1 2 G
/sheet3 3 C
SD_WP
/sheet1 4 C
/sheet1 2 G
/sheet3 3 D
/sheet3 8 C
SPI2_CS
/sheet5 7 C
/sheet3 3 B
SPI2_DI
/sheet1 2 F
/sheet7 11 F
USC4
/sheet1 2 D
/sheet1 2 F
/sheet7 11 F
USC5
/sheet1 4 B
SYNC
/sheet1 2 C
/sheet1 2 E
/sheet5 10 C
/sheet2 5 E
TP_E NV
/sheet1 4 C
/sheet1 3 G
TXD 0
/sheet1 2 B
/sheet1 2 E
/sheet2 9 B
TXD0_I
/sheet2 7 B
/sheet2 10 B
/sheet2 5 B
TXD 1
/sheet1 2 B
/sheet1 2 E
/sheet3 2 B
/sheet2 5 E
TXD1_I
/sheet3 5 B
/sheet2 10 D
/sheet5 7 D
/sheet4 15 A
/sheet4 15 C
/sheet4 2 B
/sheet3 2 B
/sheet3 9 C
/sheet2 9 C
/sheet2 6 B
USB_DN
/sheet1 4 B
/sheet1 5 C
/sheet1 3 F
USB_DP
/sheet1 4 B
/sheet1 5 D
/sheet1 3 G
USC0
/sheet1 2 C
/sheet1 2 F
/sheet7 11 F
USC1
/sheet1 2 C
/sheet1 2 F
/sheet7 11 F
/sheet2 9 B
USC2
/sheet1 2 C
/sheet1 2 F
/sheet7 11 F
/sheet2 9 B
USC3
/sheet1 2 C
/sheet1 4 A
/sheet5 6 B
VUSB
/sheet1 7 C
/sheet1 12 C
/sheet1 12 C
/sheet1 10 C
/sheet4 5 B
/sheet1 2 F
/sheet7 11 F
USC6
/sheet1 4 B
/sheet1 2 F
/sheet7 11 F
VBAT
/sheet6 2 D
/sheet6 4 D
VBUS_B
/sheet1 7 C
/sheet1 14 A
/sheet4 1 F
VCHARGE
/sheet1 2 B
/sheet1 2 E
/sheet6 5 A
VDD
/sheet7 11 F
/sheet5 7 C
/sheet5 1 B
/sheet5 3 C
/sheet5 2 B
/sheet5 4 D
Siemens AG
DATE
USER
APPR'D
E
D
C
B
A
109
8
7
6
543
2
1
A
B
C
D
E
Figure 49: Schematic of page signals
- Hardware Description 1
- Contents 3
- Figures 4
- 0 Document History 7
- 1 Introduction 11
- 1.3 Scope of Delivery 12
- 1.4 Terms and Abbreviations 12
- 2 General Overview 14
- 2.2 System Overview 16
- Adjustable Resistors 17
- 2.4 Block Diagram 18
- 2.5 Interface Overview 19
- 3.2 Test Points 23
- 3.3 GPIO Lines 25
- Figure 9: SIM card interface 27
- Figure 11: RS-232 interfaces 29
- Table 9: Pin assignment of 1 31
- 3.6.2.1 Recommended Headset 36
- Figure 18: DAI interface 39
- 3.9 I²C Interface 43
- Figure 23: I²C interface 44
- 3.10 SD Card Interface 46
- 11 10 8 7 6 5 4 3 2 1 9 47
- 3.10.1 SD 4 Bit Mode 48
- 3.10.2 SD 1 Bit Mode 49
- 3.10.3 SPI Bus Mode 50
- 3.12 Analog Interface 53
- 3.13 Antenna Interface 55
- C400,401,405 58
- X602 pin. Function 61
- 3.14.3.2 Charging Circuit 62
- GSM module 63
- 3.14.5 Adjusting the V 64
- 4 Status LEDs 65
- 4.3 Indication of Power 67
- 4.4 Indication of I²C Lines 67
- 5.1 Overview of Switches 68
- 5.2 Overview of Jumpers 73
- Figure 48: Turn on circuit 77
- 6.1.3 Emergency Restart 78
- 7 Technical Data of DSB75 79
- ~~~~~~~~~~~~~~~ 82
- 8 Appendix 83
- APPR'D 84
- NB = not mounted 87
- NB_ = not mounted 88
- 8.3 Floor Plan of the DSB75 93
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