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Hardware Information

6-4

SIMATIC Panel PC 670 Computing Unit Equipment Manual

Edition 12/01

6.3 Hardware Address Table

In the distribution of the address areas a distinction is made between

S memory address space and

S I/O address space.

Different write/read signals (I / O WR, I / O RD, MEMR, MEMW) address these

different areas. The following tables will give you an overview of the address areas

used. Please refer to the descriptions of the individual function groups for more

details.

How memory decoding works

The Pentium II CPU has a memory address area of 64 Gbytes, of which 4 Gbytes

can be used. The CPU has 64 data lines, 33 address lines and 8 byte enable lines

(BE0 to BE7), which encode the non-available address lines A0, A1 and A2.

The CPU address bus is mapped via the PAC (system controller) to the PCI

address bus. The memory addresses of addresses 0000 0000h to 0009 FFFFh

(640 kbytes) and from address 0010 0000h to 2FFF FFFFh (768 Mbytes) are

excluded.

The ISA bridge PIIX (PCI ISA IDE Xcellerator) precisely maps the ISA address bus

once on the PCI address bus. The ISA address bus for 8 bit modules includes the

address area from A0 to A19, which corresponds to the CPU addresses 0000

0000h to 000F FFFFh (1 Mbyte).

For 16-bit ISA modules, the address bus is expanded by address lines A20 to A23

and therefore addresses from 0000 0000h to 00FF FFFFh (16 Mbytes). The

distinction between the 1 Mbyte and the 16 Mbyte ISA address areas is achieved

by special memory read/write signals which are activated only if address lines A20,

A21, A22 and A23 have logic zero level.

If address areas assigned to main memory or the PCI bus are addressed by the

CPU, no ISA bus control signals are generated. This means that an ISA bus

module is not addressed in these memory areas. Conversely, an ISA bus master

cannot reach addresses above 16 Mbytes. In order to obtain a larger address area

for dual-port RAM expansions than the memory address between 640 kbytes and

1 Mbyte, various decoding holes are provided on the Pentium PU basic board:

S The CPU address area FFF0 0000h to FFFD FFFFh (1024 k-128 k BIOS =

896 Kbytes) is mapped to the ISA address area 00F0 0000h to 00FD FFFFh

and is always addressed in the CPU address area. Decoding of the address

lines A24 to A31 missing on the ISA bus is accomplished by special hardware

on the basic board.

S The CPU address area 00F0 0000h to 00FF FFFFh is mapped in the ISA

address area 00F0 0000h to 00FF FFFFh (16 MB memory window). This

setting can be enabled and disabled by running Setup.

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