
Device Specifications
C501
Semiconductor Group 10-10
AC Characteristics for C501-L40 / C501-1R40 (cont’d)
External Data Memory Characteristics
External Clock Drive Characteristics
Parameter Symbol Limit Values Unit
40 MHz
Clock
Variable Clock
1/
t
CLCL
= 3.5 MHz to 40 MHz
min. max. min. max.
RD
pulse width t
RLRH
120 – 6 t
CLCL
– 30 – ns
WR
pulse width t
WLWH
120 – 6 t
CLCL
– 30 – ns
Address hold after ALE
t
LLAX2
10 – t
CLCL
– 15 – ns
RD
to valid data in t
RLDV
–75– 5 t
CLCL
– 50 ns
Data hold after RD
t
RHDX
0–0–ns
Data float after RD
t
RHDZ
–38– 2 t
CLCL
– 12 ns
ALE to valid data in
t
LLDV
– 150 – 8 t
CLCL
– 50 ns
Address to valid data in
t
AVDV
– 150 – 9 t
CLCL
– 75 ns
ALE to WR
or RD t
LLWL
60 90 3 t
CLCL
– 15 3 t
CLCL
+ 15 ns
Address valid to WR
or RD t
AVWL
70 – 4 t
CLCL
– 30 – ns
WR
or RD high to ALE high t
WHLH
10 40 t
CLCL
– 15 t
CLCL
+ 15 ns
Data valid to WR
transition t
QVWX
5–t
CLCL
– 20 – ns
Data setup before WR
t
QVWH
125 – 7 t
CLCL
– 50 – ns
Data hold after WR
t
WHQX
5–t
CLCL
– 20 – ns
Address float after RD
t
RLAZ
–0–0ns
Parameter Symbol Limit Values Unit
Variable Clock
Freq. = 3.5 MHz to 40 MHz
min. max.
Oscillator period
t
CLCL
25 285.7 ns
High time
t
CHCX
10 t
CLCL
– t
CLCX
ns
Low time
t
CLCX
10 t
CLCL
– t
CHCX
ns
Rise time
t
CLCH
–10ns
Fall time
t
CHCL
–10ns
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