
Device Specification
Semiconductor Group 7-66
AC Characteristics (cont’d)
Parameter Symbol Limit values Unit
18 MHz clock Variable clock
1/t
CLCL
= 3.5 MHz to 18 MHz
min. max. min. max.
External Data Memory Characteristics
RD pulse width t
RLRH
233 – 6 t
CLCL
– 100 – ns
WR pulse width t
WLWH
233 – 6 t
CLCL
– 100 – ns
Address hold after ALE t
LLAX2
81 – 2 t
CLCL
– 30 – ns
RD to valid data in t
RLDV
– 128 – 5 t
CLCL
– 150 ns
Data hold after RD t
RHDX
0–0 – ns
Data float after RD t
RHDZ
–51– 2 t
CLCL
– 60 ns
ALE to valid data in t
LLDV
– 294 – 8 t
CLCL
– 150 ns
Address to valid data in t
AVDV
– 335 – 9 t
CLCL
– 165 ns
ALE to WR or RD t
LLWL
117 217 3 t
CLCL
– 50 3 t
CLCL
+50 ns
WR or RD high to ALE
high
t
WHLH
16 96 t
CLCL
– 40 t
CLCL
+40 ns
Address valid to WR t
AVWL
92 – 4 t
CLCL
– 130 – ns
Data valid to WR
transition
t
QVWX
11 – t
CLCL
– 45 – ns
Data setup before WR t
QVWH
239 – 7 t
CLCL
– 150 – ns
Data hold after WR t
WHQX
16 – t
CLCL
– 40 – ns
Address float after RD t
RLAZ
–0– 0 ns
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