Siemens EF 88H Series Bedienungsanleitung PDF herunterladen (Seite 34)

Semiconductor Group 4 - 9

After the on-chip oscillator finally has started, the oscillator watchdog detects the correct function;

then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in

order to allow the oscillation of the on-chip oscillator to stabilize (figure 4-4, II). Subsequently the

clock is supplied by the on-chip oscillator and the oscillator watchdog’s reset request is released

(figure 4-4, III). However, an externally applied reset still remains (figure 4-4, IV) active and the

device does not start program execution (figure 4-4, V) before the external reset is also released.

Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply

the external reset signal when powering up. The reasons are as follows:

– Termination of Hardware Power Down Mode (a HWPD

signal is overridden

by reset)

– Termination of Software Power Down Mode

– Reset of the status flag OWDS that is set by the oscillator watchdog during the

power up sequence.

The external reset signal must be hold active at least until the on-chip oscillator has started and the

internal watchdog reset phase is completed. An external reset time of more than 5 ms should be

sufficient in typical applications. If only a capacitor at pin Reset

is used a value of 100 nF provides

the desired reset time.

System Reset

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Siemens EF 88H Series Bedienungsanleitung Seite 34