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Device Specification

Semiconductor Group 7-19

Accesses to XRAM

Because the XRAM is used in the same way as external data memory the same instruction

types must be used for accessing the XRAM.

Note:

If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the

cycle which the reset is detected at (MOVX is a 2-cycle instruction):

Reset detection at cycle 1: The new value will not be written to XRAM. The old value

is not affected.

Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.

Accesses to XRAM using the DPTR

There are a Read and a Write instruction from and to XRAM which use one of the 16-bit DPTR

for indirect addressing. The instructions are:

MOVX A, @DPTR (Read)

MOVX @DPTR, A (Write)

Normally the use of these instructions would use a physically external memory. However, in the

SAB 80C517A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM

address space (DPTR F800

Accesses to XRAM using the Registers R0/R1

The 8051 architecture provides also instructions for accesses to external data memory range

which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions

are:

MOVX A, @Ri (Read)

MOVX @Ri, A (Write)

In application systems, either a real 8-bit bus (with 8-bit address) is used or Port 2 serves as

page register which selects pages of 256-byte. However, the distinction, whether Port 2 is

used as general purpose I/O or as "page address" is made by the external system design. From

the device’s point of view it cannot be decided whether the Port 2 data is used externally as

address or as I/O data!

Hence, a special page register is implemented into the SAB 80C517A to provide the possibility

of accessing the XRAM also with the MOVX @Ri instructions, i.e. XPAGE serves the same

function for the XRAM as Port 2 for external data memory.

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Siemens EF 88H Series Bedienungsanleitung Seite 81