
8-7
Ladder Logic (LAD) for S7-300 and S7-400
C79000-G7076-C504-02
8.6 Invert Power Flow
The Invert Power Flow instruction negates the RLO.
Table 8-5 Invert Power Flow Element
LAD Element Parameter Data Type Memory Area Description
NOT
None – – –
Status Word Bits
BR CC 1 CC 0 OV OS OR STA RLO FC
Write – – – – – – 1 * –
I 0.0
I 0.1 I 0.2
Q 4.0
Output Q 4.0 is 1 if one of the following
conditions exists:
S The signal state at input I 0.0 is NOT 1
S Or the signal state is NOT 1 at either
input I 0.1 or input I 0.2 or both.
NOT
Figure 8-5 Invert Power Flow
Description
Bit Logic Instructions
Kommentare zu diesen Handbüchern