
9-10
Ladder Logic (LAD) for S7-300 and S7-400
C79000-G7076-C504-02
–– t –– –– t ––
t = programmed time
If the signal state of input I 0.0 changes from 0 to
1 (that is, there is a positive edge in the RLO),
timer T 5 is started. If the specified time of two
seconds (2s) elapses and the signal state of
input I 0.0 is still 1, the signal state of output
Q 4.0 is 1. If the signal state of input I 0.0
changes from 1 to 0, the timer is stopped and
output Q 4.0 is 0 (see also Section 9.3). If the
signal state of input I 0.1 changes from 0 to 1
while the timer is running, the timer is reset.
I 0.0
T 5
S_ODT
R
Q
TV BI
BCD
S5T# 2s
I 0.1
Q 4.0
S
Status Word Bits
Timing Diagram
BR CC 1 CC 0 OV OS OR STA RLO FC
Write – – – – – x x x 1
RLO at S input
RLO at R input
Timer running
Signal state check for 1
Signal state check for 0
Figure 9-5 On-Delay S5 Timer
Timer Instructions
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