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19-3

Ladder Logic (LAD) for S7-300 and S7-400

C79000-G7076-C504-02

19.2 Exception Bit BR Memory

You can use the Exception Bit BR Memory instruction to check the signal

state of the BR (Binary Result) bit of the status word (see Section 6.3). When

used in series, this instruction combines the result of its check with the

previous result of logic operation (RLO) according to the And truth table

(see Section 6.2 and Table 6-8). When used in parallel, this instruction

combines the result of its check with the previous RLO according to the Or

truth table (see Section 6.2 and Table 6-9).

Figure 19-2 shows the Exception Bit BR Memory element and its negated

form. The elements are pictured with their international and SIMATIC short

names.

BIE

International element SIMATIC element

Figure 19-2 Exception Bit BR Memory Element and Its Negated Form

Status Word Bits

BR CC 1 CC 0 OV OS OR STA RLO FC

Write – – – – – x x x 1

I 0.0

Output Q 4.0 is set if the signal state at input

I 0.0 is 1 or the signal state at input I 0.2 is 0,

and, in addition to this RLO, the signal state

of the BR bit is 1.

Q 4.0

I 0.2

Figure 19-3 Exception Bit BR Memory

Description

The Element and

Its Negated Form

Status Bit Instructions

1 2 ... 222 223 224 225 226 227 228 229 230 231 232 ... 317 318

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