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Cycle and Response Times
9-7
ET 200S IM 151-7 CPU Interface Module
A5E00058783-04
Longest response time
The following figure shows what the longest response time consists of.
Operating
system
User
program
PII
While the PII is being read in, the status of
the observed input changes. The change in
the input signal is no longer taken into
account in the PII.
PIQ
The change in the input signal is taken
account of in the PII here.
The change in the input signal is processed
by the user program here.
The response of the user program to the
input signal change is passed on to the
outputs here.
Response time
Delay of the inputs +
2 DP cycle time at the PROFIBUS-DP
Delay of the outputs +
2 DP cycle time at the PROFIBUS-DP
Operating
system
User
program
PII
PIQ
Figure 9-3 Longest response time
Calculation
The (longest) response time consists of the following:
2 process image transfer time for the inputs +
2 process image transfer time for the outputs +
2 operating system processing time +
2 program scanning time +
4 run time of the DP slave frame (incl. processing in the DP master) +
Delay of the inputs and outputs
This corresponds to the sum of 2x cycle time and delay of the inputs and outputs
plus 4x DP cycle time.
- Drawing number 1
- Qualified Personnel 2
- Correct Usage 2
- Trademarks 2
- Safety Guidelines 2
- Purpose of the manual 3
- Required level of knowledge 3
- Guide to the manual 6
- Special note 6
- Recycling and disposal 6
- Additional support 7
- Training center 8
- A&D Technical Support 8
- A5E00058783-04 10
- Contents 11
- Product Overview 19
- What is the IM 151-7 CPU? 20
- IM 151-7 CPU 21
- ET 200S fail-safe modules 26
- Getting Started 27
- Required material and tools 28
- Return 35
- 2.6 6th step: Test Run 36
- Set the slave address to 4 38
- Click on the New button; 38
- S7-300 CPU 42
- ResultAction 43
- IM 151-7 CPU and S7-300 45
- Diagnosis and troubleshooting 48
- Other manuals 48
- Addressing 49
- Slot Assignment 50
- Address Assignment 51
- Advantages 53
- Data consistency 54
- Access in the user program 55
- Rules for address allocation 56
- Sample Program 57
- S5 DP master 58
- Introduction 59
- Equidistance 59
- DP master functionality 59
- Access to the ET 200S 61
- 4.2 Network components 64
- 4.3 PROFIBUS address 66
- 4.4 Functions via the PD/OP 67
- Force test function 68
- Application example 69
- 4.5 Direct communication 70
- ET 200S in the MPI Network 73
- Structure of an MPI network 74
- Transmission rates 74
- Network components 74
- 5.2 MPI address 75
- DP Master Module 77
- Procedure 78
- Commissioning 79
- Stand-alone (MPI) 84
- IM 151-7 CPU as S7 slave 84
- Prerequisite 85
- How do you reset the memory? 86
- Commissioning the ET 200S 89
- Loading the user program 90
- Start-up 90
- 7.4 Diagnostics using LEDs 91
- Diagnostic addresses 94
- 7.6.1 Station status 1 to 3 98
- Station status 2 99
- Station status 3 99
- 7.6.2 Master PROFIBUS address 100
- 7.6.3 Manufacturer ID 100
- 7.6.4 Module diagnostics 101
- 7.6.5 Module status 102
- Structure 103
- 7.6.6 Interrupt status 104
- Commissioning and Diagnostics 106
- In this section 107
- More detailed information 107
- Bytes 0 and 1 109
- Module classes 109
- Bytes 2 and 3 109
- Bytes 4 to 7 110
- Single fault of a channel 111
- Functions of the IM 151-7 CPU 113
- 8.1 Data for the PROFIBUS-DP 114
- Mode selector 116
- 8.3 SIMATIC Micro Memory Card 118
- Service life of an MMC 119
- 6ES7 953Ć8Lx00Ć0AA0 121
- Firmware update with MMC 122
- 8.4 Memory concept 124
- Working memory 125
- System memory 125
- Retentivity 125
- Erasing blocks 128
- Uploading 128
- Compression 129
- Promming (RAM to ROM) 129
- Removing/inserting the MMC 130
- Memory reset 131
- Restart (warm restart) 131
- 8.4.3 Address areas 132
- Cycle time 133
- Local data 134
- 8.4.4 Handling data in DBs 135
- Measured value archives 136
- MMC access 137
- 8.5 Interfaces 138
- 8.6 Clock 140
- 8.7 S7 connections 141
- Assigning S7 connections 142
- 8.8 Communication 146
- OP communication 147
- S7 basic communication 147
- S7 communication 147
- Global data communication 148
- GD resources 149
- 8.9 Routing 150
- Prerequisites 151
- More information 152
- 8.10 Data consistency 153
- 8.11 Blocks 154
- 8.12 Parameters 156
- RTD-4L Pt 100 158
- Reference 159
- Exceptions 160
- Cycle and Response Times 165
- 9.1 Cycle time 166
- Extending the cycle time 167
- Process image transfer time 167
- User program scanning time: 168
- 9.2 Response time 169
- Shortest response time 170
- Calculation 170
- Longest response time 171
- 9.3 Interrupt response time 172
- Technical Specifications 173
- Order numbers 174
- Features 174
- SFC 20 ”BLKMOV” 182
- SFC 54 ”RD_DPARM” 182
- PD/OP functions 184
- Chapter overview 187
- More information 187
- 12.2 Porting the user program 189
- Porting with packed addresses 190
- Rewiring 190
- Glossary 193
- Diagnostic buffer 195
- Diagnostic interrupt 195
- Direct Communication 195
- Distributed I/O Systems 195
- DP Master 195
- FC Function 197
- Function 197
- Transmission rate 204
- User memory 204
- User program 204
- Working Memory 204
- Product information for 211
- 147Ć1AA11Ć0XB0) 211
- 147Ć2AA01Ć0XB0) 211
- 147Ć2AB01Ć0XB0) 211
- 151Ć7AA11Ć0AB0) 211
- A5E00385826-02 212
- Copyright 2006 by Siemens AG 213
- A5E00860829-01 213
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